View NT7605-BDW01_8330895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nt7605 single-chip 20c x 2l dot-matrix lcd controller / driver 1 v2.1 features internal lcd drivers 16 common signal drivers 100 segment signal drivers maximum display dimensions 20 characters * 2 lines or 40 characters * 1 line interfaces with 4-bit or 8-bit mpu versatile display functions provided on chip: display clear, cursor home, display on/off, cursor on/off, character blinking, cursor shift, and display shift three duty factors, selected by program: 1/8, 1/11, and 1/16 displays data ram (dd ram): 80 x 8 bits (displays up to 80 characters) character generator ram (cg ram): 64 x 8 bits for general data, 8 5 x 8 programmable dot patterns, or 4 5 x 10 programmable dot patterns low voltage reset ito option for a-type and b-type lcd waveform 2 kinds of lcd pads sequence character generator rom (cg rom): 2 kinds of cg rom sizes: 192 characters: 160 5 x 8 dot patterns 32 5 x 10 dot patterns 240 characters: 192 5 x 8 dot patterns 48 5 x 10 dot patterns custom cg rom is also available built-in power-on reset function logic power supply: 2.8v ~ 5.5v lcd driver power supply: v1 ~ v5 divided by built-in lcd power division resister. two oscillator operations (freq. = 500khz - 540khz): ? built-in rc oscillation ? external clock cmos process available in cog form general description the nt7605 is a dot matrix lcd controller and driver lsi that can operate with either a 4-bi t or an 8-bit microprocessor (mpu). nt7605 receives control character codes from the mpu, stores them in an inter nal ram (up to 80 characters), transforms each character code into a 5 x 7, 5 x 8, or 5 x 10 dot matrix character pattern, and then displays the codes on the lcd panel. the built-in character generator rom consists of 256 different character patterns. the nt7605 also contains char acter generator ram where the user can store 8 different character patterns at run time. these memory features make t he character display flexible. nt7605 also provides many disp lay instructions to achieve versatile lcd display functi ons. the nt7605 is fabricated on a single lsi chip using the cmos process, resulting in very low power requirements.
nt7605 2 pad configuration 12 1 163 64 65 nt7605 11 13 14 26 27 29 30 38 45 82 83 162 180 5600 m 1230 m 39 44 size item pad no. x y unit chip size - 1230 5600 pad pitch 1 - 180 65 m
nt7605 3 block diagram i/o buffer v 1 v 2 v 3 v 4 v 5 rs r/w e db7 ~ db4 db3 ~ db0 4 4 instruction register (ir) 8 instruction decode 8 address counter v dd gnd osc1 osc2 timing generator data register (dr) busy flag (bf) 8 7 7 character generator ram (cg ram) 64 x 8 bits cursor address counter display data ram (dd ram) 80 x 8 bits 16-bit shift register common signal driver 7 cursor /blink controller 7 7 7 lcd driver voltage generator 16 8 8 character generator rom (cg rom) 8 16 com1 i com16 100-bit latch circuit segment signal driver 100 100 seg1 i seg100 paraller - to - serial converter 5 5 testm 7 opt_ud opt_r0 opt_r1 opt_lcd test testd
nt7605 4 pad description ( total 180 pads for cog type) pad no. designation i/o external connection description 1 test i test pin test pin internally pull-down. (no connect for user) 2 testm o test output lcd driver clock output. (no connect for user) 3 - 11 gnd p power supply gnd: 0v 12 osc1 i for external clock operati on, clock inputs to osc1 13 osc2 o clock output 14, 15 v1 p power supply power supply for lcd driver. v dd v1 v2 v3 v4 v5 gnd 16, 17 v2 p power supply power supply for lcd driver 18, 19 v3 p power supply power supply for lcd driver 20, 21 v4 p power supply power supply for lcd driver 22 - 26 v5 p power supply power supply for lcd driver 27, 29 opt_r0, opt_r1 i ito option the built-in bias resister select: opt_r1, opt_r0: no ito = 1. ito on = 0 1, 1: 2.2k ; 1, 0: 4k ; 0, 1: 6.8k ; 0, 0: no built-in bias resister: 30 - 38 v dd p power supply v dd : +5v 30, 40 rs i mpu register select signal 0: instruction register (write), busy flag, address counter (read) 1: data register (write, read) 41, 42 r/w i mpu read/write control signal 0: write 1: read 43, 44 e i mpu read/write start signal (schmitt trigger input) 45, 46 db0 47, 48 db1 49, 50 db2 51, 52 db3 i/o mpu lower 4 tri-state bi-directional data bus for transmitting data between mpu and nt7605. not us ed during 4-bit operation 53, 54 db4 55, 56 db5 57, 58 db6 59, 60 db7 i/o mpu higher 4 tri-state bi-directional data bus for transmitting data between mpu and nt7605. db7 is also used as busy flag 61 opt_lcd i ito option no ito. (option = 1): b-type waveform ito on. (option = 0): a-type waveform 63 opt_ud i ito option no ito. (option = 1): com1 com8 com9 com16; seg1 seg100 ito on. (option = 0): com9 com16 com1 com8; seg100 seg1 64 testd o test output test data output. (no connect for user) 180 - 173 com1 - 8 o lcd panel 65 - 72 com9 - 16 o lcd panel common signal output pins, for place on the upper glass (opt_ud=1) 65 - 72 com1 - 8 o lcd panel 180 - 173 com9 - 16 o lcd panel common signal output pins, for place on the lower glass (opt_ud=0) 172 - 73 seg1 - 100 o lcd panel segment signal output pins (opt_ud = 1) 73 - 172 seg1 - 100 o lcd panel segment signal output pins (opt_ud = 0) 28, 62 gnd_out p gnd output pin, use for pull-down ito option
nt7605 5 functional description the nt7605 is a dot-matrix lcd controller and driver lsi. it operates with either a 4-bit or an 8-bit microprocessor (mpu). the nt7605 receives both inst ructions and data from the mpu. some instructions set operation modes, such as the function mode, data entry mode, and display mode; as well as some control lcd display functions, such as clear display, restore display, shift display as well as controlling the cursor. other instructions include reading and writing both data and addresses. all the instructi ons allow users convenient and powerful functions to control the lcd dot-matrix displays. data is written into and read from the data display ram (dd ram) or the character generator ram (cg ram). as display character codes, t he data stored in the dd ram decodes a set of dot-matrix char acter patterns that are built into the character generat or rom (cg rom). the cg rom, with many character patterns (up to 256 patterns), defines the character pattern fonts. the nt7605 regularly scans the character patterns through the segment drivers. the cg ram stores character pa ttern fonts at run time if users intend to show characte r patterns that are not defined in the cg rom. this feat ure makes character display flexible. other unused bytes can be used as general-purpose data storage. the lcd driver circuit consis ts of 16 common signal drivers and 100 segment signal driver s allowing a variety of application configurations to be implemented. character generator rom (cg rom) the character generator rom generates lcd dot character patterns from the 8-bit character pattern codes. the nt7605 provides 2 cg rom configurations: 1. 192 characters: the cg rom contains 160 5 x 8 dot character patterns and 32 5 x 10 dot character pattern s. the relation between the character codes and character patterns is shown in table 1. the character codes from 00h to 0fh are used to get character patterns from the cg ram. the character codes 10h to 1fh, 80h to 9fh and 20h all map to null character patterns. the character codes from e0h to ffh are assigned to generate 5 x 10 dot character patterns, and other codes are used to generate 5x8 dot character patterns. 2. 240 characters: the cg rom contains 192 5 x 8 dot character patterns and 48 5 x 10 dot character pattern s. the relation between the character codes and character patterns is shown in table 2. the character codes from 00h to 0fh are used to get character patterns from the cg ram. the character codes from 10h to 1fh and from e0h to ffh are assigned to generate 5 x 10 dot character pa tterns, and other codes to generate 5 x 8 dot character patterns. only one null character pattern exists in th is type. note that the underlined cursor, displayed on the 8th dut y may be obscure if the 8th row of a dot character pattern is coded. we recommend that users display the cursor in t he blinking mode if coding 5 x 8 dot character patterns is their custom cg rom. custom character patterns are available by mask-programming the rom. fo r convenience of character pattern development, novatek has developed a user-friendly editor program for the nt7605 to help determine the character patterns users prefer. by executing the program on the computer , users can easily create and modify their character patterns. by transferring the resulting files generated by the program through a modem or some other communication method, the user and novatek can establish a reliable, fast lin k for programming the cg rom.
nt7605 6 absolute maximum ratings* power supply voltage (v dd ) . . . . . . . . . . -0.3v to +7.0v power supply voltage (v 1 to v 5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v dd + 0.3v input voltage (v i ) . . . . . . . . . . . . . . .-0.3v to v dd + 0.3v operating temperature (t opr ) . . . . . . .-20 c to +70 c storage temperature (t stg ) . . . . . . . .-55 c to +125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of th is specification is not implied or intended. exposure to t he absolute maximum rating conditions for extended periods may affect device reliability. all voltage values are referenced to gnd = 0v v 1 to v 5 , must maintain v dd v 1 v 2 v 3 v 4 v 5 gnd dc electrical characteristics (v dd = 4.5v~5.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions applicable pin v dd operating voltage 4.5 5.0 5.5 v v ih1 "h" level input voltage 0.8 v dd - v dd v v il1 "l" level input voltage -0.3 - 0.2 v dd v db0 - db7, rs, r/w, e, osc1 v oh1 "h" level output voltage v dd - 0.6 - - v i oh = -1.2ma v ol1 "l" level output voltage - - gnd + 0.6 v i ol = 1.2ma db0 - db7 (cmos) v comd driver voltage descending (com) - - 0.3 v i d = 5 a com1 - 16 v segd driver voltage descending (seg) - - 0.3 v i d = 5 a seg1 - 100 i il input leakage current -1 - 1 a v in = 0 to v dd -i p pull-up mos current 50 125 250 a v dd = 5v rs, r/w, db0 - db7 i op power supply current - 1 1.5 ma rf oscillation, from external clock v dd = 5v, f osc = f cp = 540khz, include lcd bias current v dd external clock operation f cp external clock operating frequency 380 540 750 khz t duty external clock duty cycle 45 50 55 % t rcp external clock rise time 0.1 - 0.5 s t fcp external clock fall time 0.1 - 0.5 s internal clock operation (built-in rc oscillator) f osc oscillator frequency 380 540 750 khz rf = 50k ? (reference only) v dd = 2 .8v ~ 5.5v v lcd lcd driving voltage 3.0 - v dd v v dd - v 5
nt7605 7 dc electrical characteristics (continued) (v dd = 2.8v~4.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions applicable pin v dd operating voltage 2.8 3.0 4.5 v v ih1 "h" level input voltage 0.8 v dd - v dd v v il1 "l" level input voltage -0.3 - 0.2 v dd v db0 - db7, rs, r/w, e, osc1 v oh1 "h" level output voltage v dd - 0.4 - - v i oh = -0.8ma v ol1 "l" level output voltage - - gnd + 0.4 v i ol = 0.8ma db0 - db7 (cmos) v comd driver voltage descending (com) - - 0.3 v i d = 5 a com1 - 16 v segd driver voltage descending (seg) - - 0.3 v i d = 5 a seg1 - 100 i il input leakage current -1 - 1 a v in = 0 to v dd -i p pull-up mos current 30 75 150 a v dd = 3v rs, r/w, db0 - db7 i op supply current power supply current - 1 1.5 ma rf oscillation, from external clock v dd = 3v, f osc = f cp = 540khz, include lcd bias current v dd external clock operation f cp external clock operating frequency 380 540 750 khz t duty external clock duty cycle 45 50 55 % t rcp external clock rise time 0.1 - 0.5 s t fcp external clock fall time 0.1 - 0.5 s internal clock operation (built-in rc oscillator) f osc oscillator frequency 380 540 750 khz rf = 50k ? (reference only) v dd = 2 .8v ~ 5.5v v lcd lcd driving voltage 2.5 - v dd v v dd - v 5
nt7605 8 ac characteristics read cycle (v dd = 4.5v~5.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 1 t whe enable "h" level pulse width 300 - - ns figure 1 t re , t fe enable rise/fall time - - 25 ns figure 1 60 1 - - t as rs, r/w setup time 100 2 ns figure 1 t ah rs, r/w address hold time 10 - - ns figure 1 t rd read data output delay - - 190 ns figure 1 t dhr read data hold time 20 - - ns figure 1 write cycle (v dd = 4.5v~5.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 2 t whe enable "h" level pulse width 300 - - ns figure 2 t re , t fe enable rise/fall time - - 25 ns figure 2 60 1 - - ns figure 2 t as rs, r/w setup time 100 2 t ah rs, r/w address hold time 10 - - ns figure 2 t ds data output delay 100 - - ns figure 2 t dhw data hold time 10 - - ns figure 2 notes: 1: 8-bit operation mode 2: 4-bit operation mode power supply conditions using internal reset circuit (v dd = 4.5v~5.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t ron power supply rise time 0.1 - 10 ms figure 3 t off power supply off time 1 - - ms figure 3
nt7605 9 ac characteristics (continued) read cycle (v dd = 2.8v~4.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 1 t whe enable "h" level pulse width 300 - - ns figure 1 t re , t fe enable rise/fall time - - 25 ns figure 1 60 1 - - ns figure 1 t as rs, r/w setup time 100 2 t ah rs, r/w address hold time 10 - - ns figure 1 t rd read data output delay - - 190 ns figure 1 t dhr read data hold time 20 - - ns figure 1 write cycle (v dd = 2.8v~4.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 2 t whe enable "h" level pulse width 300 - - ns figure 2 t re , t fe enable rise/fall time - - 25 ns figure 2 60 1 - - ns figure 2 t as rs, r/w setup time 100 2 t ah rs, r/w address hold time 10 - - ns figure 2 t ds data output delay 150 - - ns figure 2 t dhw data hold time 10 - - ns figure 2 notes: 1: 8-bit operation mode 2: 4-bit operation mode power supply conditions using internal reset circuit (v dd = 2.8v~4.5v, gnd = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t ron power supply rise time 0.1 - 10 ms figure 3 t off power supply off time 1 - - ms figure 3
nt7605 10 timing waveforms read operation rs r/w e db0 ~ db7 v ih1 v il1 t re t rd v oh1 v ol1 vaild data v ih1 v il1 t as v ih1 v il1 t ah t whe t fe v il1 t dhr v oh1 v ol1 t cyce v il1 figure 1. bus read operation sequence (reading out data from nt7605 to mpu) write operation rs r/w e db0 ~ db7 v ih1 v il1 t re t ds v ih1 v il1 vaild data v ih1 v il1 t as v ih1 v il1 t ah t whe t fe v il1 t dhw v ih1 v il1 t cyce v il1 v il1 figure 2. bus writ e operation sequence (writing data from mpu to nt7605) interface signals with segment driver lsi v dd 0.2v t ron 4.5v 0.1ms > t ron > 10ms t off 0.2v 0.2v t off > 1ms figure 3. t off stipulates the time of power off for instantaneous power supply to or when power supply repeats on and off.
nt7605 11 note 1: the nt7605 has two clock options: a. internal oscillator (built-in rc) osc1 osc2 open open b. external clock operation osc1 osc2 open pulse input note 2: input/output terminals: a. input terminal applicable terminal: e (no pull up mos) pmos v dd nmos applicable terminal: rs, r/w (with pull up mos) pmos v dd nmos v dd pmos pull up mos
nt7605 12 b. output terminal applicable terminal: testm pmos v dd nmos c. i/o terminal applicable terminal: db0 to db7 nmos v dd pmos pull up mos pmos v dd pmos v dd nmos enable data (output circuit) (tristate) note 3: ito options: set option = 0: place ito on the option pad. set option = 1: no ito on the option pad. gnd_out option pad option (internal pull up) option = 1 no ito: option pad ito on: ito option = 0 option (internal pull up) gnd output pad gnd output pad gnd_out
nt7605 13 table 1. nt7605h-bdt01 corres pondence between character c odes and character patterns (novatek standard 192 character cg rom)
nt7605 14 instruction set code execution time (max) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 function (f osc = 540khz) display clear 0 0 0 0 0 0 0 0 0 1 clear entire display area, restore display from shift, and load address counter with dd ram address 00h 1.64ms display/ cursor home 0 0 0 0 0 0 0 0 1 * restore display from shift and load address counter with dd ram address 00h 1.64ms entry mode set 0 0 0 0 0 0 0 1 i/d s specify direction of cursor movement and display shift mode. this operation takes place after each data transfer (read/write) 40 s display on/off 0 0 0 0 0 0 1 d c b specify activation of display (d) cursor (c) and blinking of character at cursor position (b) 40 s display/ cursor shift 0 0 0 0 0 1 s/c r/l * * shift display or move cursor 40 s function set 0 0 0 0 1 dl n f * * set interface data length (dl), number of the display line (n), and character font (f) 40 s ram address set 0 0 0 1 acg load the address counter with a cg ram address subsequent data access is for cg ram data 40 s dd ram address set 0 0 1 add load the address counter with a dd ram address subsequent data access is for dd ram data 40 s busy flag/ address counter read 0 1 bf ac read busy flag (bf) and contents of address counter (ac) 1 s cg ram/ dd ram data write 1 0 write data write data to cg ram or dd ram 40 s cg ram/ dd ram data read 1 1 read data read data from cg ram or dd ram 40 s i/d = 1 : increment i/d = 0 : decrement s = 1 : display shift on d = 1 : display on c = 1 : cursor display on b = 1 : cursor blink on s/c = 1 : shift display s/c = 0 : move cursor r/l = 1 : shift right r/l = 0 : shift left dl = 1 : 8-bit dl = 0 : 4-bit n = 1 : dual line n = 0 : signal line f = 1 : 5x10 dots f = 0 : 5x8 dots bf = 1 : internal operation bf = 0 : ready for instruction dd ram : display data ram cg ram : character generator ram acg : character generator ram address add : display data ram address ac : address counter note 1: symbol " * " signifies an insignificant bit (disregard). note 2: correct input value for "n" is predetermined for each model. note 3: the variation of execution time depends on the change of oscillator frequency; for example: if fosc = 380khz, then execution time = 40 s (540khz / 380khz) = 57 s
nt7605 15 interface to lcd (1) character font and number of lines the nt7605 provides a 5 x 7 dot char acter font 1-line mode, a 5 x 10 dot character font 1-line mode and a 5 x 7 dot character font 2-line m ode, as shown in the table below. three types of common signals are available as displayed in t he table. the number of lines and the font type can be selected by the program. number of lines character font number of common signals duty factor bias 1 5 x 7 dots + cursor (or 5 x 8 dots) 8 1/8 1/4 1 5 x 10 dots + cursor 11 1/11 1/4 2 5 x 7 dots + cursor (or 5 x 8 dots) 16 1/16 1/5 (2) connection to lcd the following 4 lcd connection examples show the va rious combinations between characters and lines. nt7605 can directly drive the following combinations: (a) 5 x 8 font ? 20 characters x 1 line (1/8 duty cycle, 1/4 bias) nt7605 com1 com8 seg1 seg100 lcd panel
nt7605 16 (b) 5 x 10 font - 20 characters x 1 line (1/11 duty cycle, 1/4 bias) nt7605 com1 com8 seg1 seg100 lcd panel com11 com9 (c) 5 x 8 font - 20 characters x 2 line (1/16 duty cycle, 1/5 bias) nt7605 com1 com8 seg1 seg100 lcd panel com16 com9
nt7605 17 (d) 5 x 8 font - 40 characters x 1 line (1/16 duty cycle, 1/5bias) nt7605 com1 com8 seg1 seg100 lcd panel com16 com9
nt7605 18 (3) orientation type of nt7605: 1 type2: place the chip on the lower glass(ic face down) opt_ud = 0 ( ito on) lcd panel c1, s1 c16, s100 nt7605 c9, s100 c8, s1 type1: place the chip on the upper glass(ic face up) opt_ud = 1 (no ito) nt7605 1 lcd panel c1, s1 c16, s100 c8, s1 c9, s100 1 lcd panel c16, s100 c1, s1 nt7605 c8, s1 c9, s100 type4: place the chip on the upper glass(ic face up) opt_ud = 0 ( ito on) 1 lcd panel c16, s100 c1, s1 nt7605 c8, s1 c9, s100 type3: place the chip on the lower glass(ic face down) opt_ud = 1 (no ito) note: 1. dot line: ito layout on lower glass. 2. dash line: ito layout on upper glass.
nt7605 19 (3) bias power connection nt7605 provides 1/4 or 1/5 bias for vari ous duty cycle applications. the built-in pow er division resister divide voltage is described in the following table. the connection of nt7605, power supply, and re sistors are also shown as follows: power division 1/8, 1/11 duty cycle - 1/4 bias 1/16 duty cycle - 1/5 bias v 1 v dd - 1/4 v lcd v dd - 1/5 v lcd v 2 v dd - 1/2 v lcd v dd - 2/5 v lcd v 3 v dd - 1/2 v lcd v dd - 3/5 v lcd v 4 v dd - 3/4 v lcd v dd - 4/5 v lcd v 5 v dd - v lcd v dd - v lcd the bias is auto selected by the duty cycle. when the lcd is set to 1/16 duty, the bias is set to 1/5. otherwise, the bias is s et to 1/4. the ito option can select the division resister value: opt_r1 opt_r0 division resister no ito (1) no ito (1) 2.2k no ito (1) ito on (0) 4k ito on (0) no ito (1) 6.8k ito on (0) no ito (0) no built-in resister (external input) nt7605 v dd v 1 v 2 v 3 v 4 v 5 v dd vr gnd v lcd built-in bias resister 2.2k, 4k or 6.8k ohm nt7605 v dd v 1 v 2 v 3 v 4 v 5 vr gnd v dd r r r r v lcd nt7605 v dd v 1 v 2 v 3 v 4 v 5 vr v dd r r r r r v lcd exit power division. (the resistance value depends on the lcd panel size) gnd
nt7605 20 (4) lcd waveform a-type, 1/8 duty cycle, 1/4 bias com1 v dd v 1 v 2 (v 3 ) v 4 v 5 1234 5 800 clocks 812 1 frame 11.9ms = 8 800 540k 1sec = frame 1 hz 3 . 84 = ms 9 . 11 1 = frequency frame a-type, 1/11 duty cycle, 1/4 bias com1 v dd v 1 v 2 (v 3 ) v 4 v 5 1234 5 800 clocks 11 1 2 1 frame 16.3ms = 11 800 540k 1sec = frame 1 61.4hz = 16.3ms 1 = frequency frame a-type, 1/16 duty cycle, 1/5 bias com1 v dd v 1 v 2 v 4 v 5 1234 5 400 clocks 16 1 2 1 frame 11.9ms = 16 400 540k 1sec = frame 1 84.3hz = 11.9ms 1 = frequency frame v 3
nt7605 21 b-type, 1/8 duty cycle, 1/4 bias com1 v dd v1 v2 (v3) v4 v5 1234 9 800 clocks 1 frame 11.9ms 8 800 540k 1sec frame 1 = = 84.3hz 11.9ms 1 frequency frame = = 5678 16 2 1 b-type, 1/11 duty cycle, 1/4 bias com1 v dd v1 v2 (v3) v4 v5 1234 9 800 clocks 1 frame 16.3ms 11 800 540k 1sec 1frame = = 61.4hz 16.3ms 1 frequency frame = = 5678 22 2 1 10 11 12 21 b-type, 1/16 duty cycle, 1/5 bias com1 v dd v1 v2 v4 v5 1234 400 clocks 1 frame 11.9ms 16 400 540k 1sec 1frame = = 84.3hz 11.9ms 1 frequency frame = = 5 32 2 1 15 16 17 31 14 13 v3
nt7605 22 low voltage reset the low voltage reset function is used to monitor the supply vo ltage and applies an internal reset at the time when a low volta ge is detected. functions of the low voltage reset circuit the low voltage reset circuit has the following functions: generates an internal reset signal when v dd v lvr . cancels the internal reset signal when v dd > v lvr . here, v dd : power supply voltage, v lvr : low voltage reset detec tion voltage, about 2.0v. application circuit (for reference only) nt7605 com1 ~ 16 seg1 ~ 100 lcd panel v5 db0 ~ 7 e, r/w, rs mpu vr gnd v dd
nt7605 23 example (for reference only) interface with 8-bit mpu rs r/w e db7 internal signal busy busy no busy data data internal operation instruction busy flag check instruction interface with 4-bit mpu rs r/w e db7 internal signal no busy d7 internal operation instruction busy flag check instruction d3 ac3 d7 d3 ac3 busy
nt7605 24 initializing by instruction 1. 8-bit interface power on wait for more than 30 ms after vdd on function set 0 0 db7 0 0 rw rs db6 1 db5 1 db4 n db3 f db2 x db1 x db0 n 1 0 1-line mode 2-line mode f 1 0 5 x 7 dots 5 x 10 dots wait for more than 40 s display on/off control 0 0 db7 0 0 rw rs db6 0 db5 0 db4 1 db3 d db2 c db1 b db0 wait for more than 40 s d 1 0 display off display on c 1 0 cursor off cursor on b 1 0 blink off blink on clear display 0 0 db7 0 0 rw rs db6 0 db5 0 db4 0 db3 0 db2 0 db1 1 db0 wait for more than 1.64ms entry mode set 0 0 db7 0 0 rw rs db6 0 db5 0 db4 0 db3 1 db2 i/d db1 s db0 initialization end i/d 1 0 decrement mode increment mode s 1 0 entire shift off entire shift on write date to ddram: write n 1 0 db7 0 1 rw rs db6 0 db5 0 db4 1 db3 1 db2 1 db1 0 db0 ..........
nt7605 25 2. 4-bit interface power on wait for more than 30 ms after vdd on function set 0 0 db7 0 0 rw rs db6 1 db5 0 db4 x db3 x db2 x db1 x db0 n 1 0 1-line mode 2-line mode f 1 0 5 x 7 dots 5 x 10 dots wait for more than 40 s display on/off control 0 0 db7 0 0 rw rs db6 0 db5 0 db4 db3 db2 db1 db0 wait for more than 40 s d 1 0 display off display on c 1 0 cursor off cursor on b 1 0 blink off blink on clear display 0 0 db7 0 0 rw rs db6 0 db5 0 db4 db3 db2 db1 db0 wait for more than 1.64ms entry mode set 0 0 db7 0 0 rw rs db6 0 db5 0 db4 db3 db2 db1 db0 initialization end i/d 1 0 decrement mode increment mode s 1 0 entire shift off entire shift on write date to ddram: write n 1 0 db7 0 1 rw rs db6 0 db5 0 db4 db3 db2 db1 db0 .......... 0 0 0 0 1 0 x x x x 0 0 n f x x x x x x 0 0 1 d c b x x x x x x x x x x x x 0 0 0 0 0 1 x x x x x x x x 0 0 0 0 i/d s x x x x 1 0 1 1 1 0 x x x x x x x x ?
nt7605 26 ordering information part no. cg rom package shipment style nt7605h-bdb01 192 cgrom (ref p13) cog chip form bumped die on blue tape nt7605h-bdt01 192 cgrom (ref p13) cog chip form bumped die on chip tray NT7605-BDW01 192 cgrom (ref p13) cog chip form bumped die on wafer
nt7605 27 bonding diagram 12 1 163 64 65 nt7605 ( 0 , 0 ) x y 11 13 14 26 27 29 30 38 45 82 83 162 180 5600 m 1230 m 39 44 pad no. designation x y pad no. designation x y 1 test -2567.5 -546.25 31 v dd -357.5 -546.25 2 testm -2502.5 -546.25 32 v dd -292.5 -546.25 3 gnd -2437.5 -546.25 33 v dd -227.5 -546.25 4 gnd -2372.5 -546.25 34 v dd -162.5 -546.25 5 gnd -2307.5 -546.25 35 v dd -97.5 -546.25 6 gnd -2242.5 -546.25 36 v dd -32.5 -546.25 7 gnd -2177.5 -546.25 37 v dd 32.5 -546.25 8 gnd -2112.5 -546.25 38 v dd 97.5 -546.25 9 gnd -2047.5 -546.25 39 rs 552.5 -546.25 10 gnd -1982.5 -546.25 40 rs 617.5 -546.25 11 gnd -1917.5 -546.25 41 rw 682.5 -546.25 12 osc1 -1787.5 -546.25 42 rw 747.5 -546.25 13 osc2 -1722.5 -546. 25 43 e 812.5 -546.25 14 v 1 -1592.5 -546.25 44 e 877.5 -546.25 15 v 1 -1527.5 -546.25 45 db0 1332.5 -546.25 16 v 2 -1462.5 -546.25 46 db0 1397.5 -546.25 17 v 2 -1397.5 -546.25 47 db1 1462.5 -546.25 18 v 3 -1332.5 -546.25 48 db1 1527.5 -546.25 19 v 3 -1267.5 -546.25 49 db2 1592.5 -546.25 20 v 4 -1202.5 -546.25 50 db2 1657.5 -546.25 21 v 4 -1137.5 -546.25 51 db3 1722.5 -546.25 22 v 5 -1072.5 -546.25 52 db3 1787.5 -546.25 23 v 5 -1007.5 -546.25 53 db4 1852.5 -546.25 24 v 5 -942.5 -546.25 54 db4 1917.5 -546.25 25 v 5 -877.5 -546.25 55 db5 1982.5 -546.25 26 v 5 -812.5 -546.25 56 db5 2047.5 -546.25 27 opt_r0 -682.5 -546. 25 57 db6 2112.5 -546.25 28 gnd_out -617.5 -546. 25 58 db6 2177.5 -546.25 29 opt_r1 -552.5 -546. 25 59 db7 2242.5 -546.25 30 v dd -422.5 -546.25 60 db7 2307.5 -546.25
nt7605 28 bonding diagram (continued) pad no. designation x y pad no. designation x y 61 opt_lcd 2372.5 -546. 25 101 seg72 1397.5 546.25 62 gnd_out 2437.5 -546. 25 102 seg71 1332.5 546.25 63 opt_ud 2502.5 -546.25 103 seg70 1267.5 546.25 64 testd 2567.5 -546.25 104 seg69 1202.5 546.25 65 com9 2731.5 -552.5 105 seg68 1137.5 546.25 66 com10 2731.5 -487.5 106 seg67 1072.5 546.25 67 com11 2731.5 -422.5 107 seg66 1007.5 546.25 68 com12 2731.5 -357.5 108 seg65 942.5 546.25 69 com13 2731.5 -292.5 109 seg64 877.5 546.25 70 com14 2731.5 -227.5 110 seg63 812.5 546.25 71 com15 2731.5 -162.5 111 seg62 747.5 546.25 72 com16 2731.5 -97.5 112 seg61 682.5 546.25 73 seg100 2731.5 -32.5 113 seg60 617.5 546.25 74 seg99 2731.5 32.5 114 seg59 552.5 546.25 75 seg98 2731.5 97.5 115 seg58 487.5 546.25 76 seg97 2731.5 162.5 116 seg57 422.5 546.25 77 seg96 2731.5 227.5 117 seg56 357.5 546.25 78 seg95 2731.5 292.5 118 seg55 292.5 546.25 79 seg94 2731.5 357.5 119 seg54 227.5 546.25 80 seg93 2731.5 422.5 120 seg53 162.5 546.25 81 seg92 2731.5 487.5 121 seg52 97.5 546.25 82 seg91 2731.5 552.5 122 seg51 32.5 546.25 83 seg90 2567.5 546.25 123 seg50 -32.5 546.25 84 seg89 2502.5 546.25 124 seg49 -97.5 546.25 85 seg88 2437.5 546.25 125 seg48 -162.5 546.25 86 seg87 2372.5 546.25 126 seg47 -227.5 546.25 87 seg86 2307.5 546.25 127 seg46 -292.5 546.25 88 seg85 2242.5 546.25 128 seg45 -357.5 546.25 89 seg84 2177.5 546.25 129 seg44 -422.5 546.25 90 seg83 2112.5 546.25 130 seg43 -487.5 546.25 91 seg82 2047.5 546.25 131 seg42 -552.5 546.25 92 seg81 1982.5 546.25 132 seg41 -617.5 546.25 93 seg80 1917.5 546.25 133 seg40 -682.5 546.25 94 seg79 1852.5 546.25 134 seg39 -747.5 546.25 95 seg78 1787.5 546.25 135 seg38 -812.5 546.25 96 seg77 1722.5 546.25 136 seg37 -877.5 546.25 97 seg76 1657.5 546.25 137 seg36 -942.5 546.25 98 seg75 1592.5 546.25 139 seg35 -1007.5 546.25 99 seg74 1527.5 546.25 139 seg34 -1072.5 546.25 100 seg73 1462.5 546.25 140 seg33 -1137.5 546.25
nt7605 29 bonding diagram (continued) pad no. designation x y pad no. designation x y 141 seg32 -1202.5 546.25 162 seg11 -2567.5 546.25 142 seg31 -1267.5 546.25 163 seg10 -2731.5 552.5 143 seg30 -1332.5 546.25 164 seg9 -2731.5 487.5 144 seg29 -1397.5 546.25 165 seg8 -2731.5 422.5 145 seg28 -1462.5 546.25 166 seg7 -2731.5 357.5 146 seg27 -1527.5 546.25 167 seg6 -2731.5 292.5 147 seg26 -1592.5 546.25 168 seg5 -2731.5 227.5 148 seg25 -1657.5 546.25 169 seg4 -2731.5 162.5 149 seg24 -1722.5 546.25 170 seg3 -2731.5 97.5 150 seg23 -1787.5 546.25 171 seg2 -2731.5 32.5 151 seg22 -1852.5 546.25 172 seg1 -2731.5 -32.5 152 seg21 -1917.5 546.25 173 com8 -2731.5 -97.5 153 seg20 -1982.5 546.25 174 com7 -2731.5 -162.5 154 seg19 -2047.5 546.25 175 com6 -2731.5 -227.5 155 seg18 -2112.5 546.25 176 com5 -2731.5 -292.5 156 seg17 -2177.5 546.25 177 com4 -2731.5 -357.5 157 seg16 -2242.5 546.25 178 com3 -2731.5 -422.5 158 seg15 -2307.5 546.25 179 com2 -2731.5 -487.5 159 seg14 -2372.5 546.25 180 com1 -2731.5 -552.5 160 seg13 -2437.5 546.25 alk_l -2230.95 95 161 seg12 -2502.5 546.25 alk_r 2230.95 95
nt7605 30 package information chip outline dimensions unit: m nt7605 a1 a1 m m a1 a2 a1 a2 a2 a2 m m m m m m m m m m b1 b1 b1 b1 b2 b2 m m m m m c1 c1 g g g g c2 c2 f f e d r (metal 2) e d r (metal 2) f f g g f f g g ( 0 , 0 ) x y symbol dimensions in m symbol dimensions in m a1 232.5 d 569.05 a2 164 e 520 b1 130 g 42 b2 455 f 90 c1 62.5 m 65 c2 68.75 r 35
nt7605 31 tray information 10*31 xx yy e w2 f t1 t2 section y-y d h g w1 w2 a b e f w1 t1 t2 section x-x h g c h30-230*60-33 tray outline dimensions unit: mm symbol dimensions in mm symbol dimensions in mm a 1.54 g 0.84 b 2.12 h 4.20 c 5.84 w1 76.0 d 6.14 w2 68.0 e 1.60 t1 71.0 f 1.40 t2 68.3
nt7605 32 product spec. change notice nt7605 specification revision history version content date 2.1 adding note 3 and modified fosc from 270khz to 540khz (page 14 , document mistake corrected) modify the number of clock in single duty from 400 to 800 (1/8 duty and 1/11 duty),200 to 400(1/ 16 duty) and fosc from 270k to 540k(page 21) ( document mistake corrected) jul.2002 2.0 rom table deleted(page 14) b-type waveform modified(page 21 , document mistake corrected) apr.2002 1.0 add new orientation type of nt7605 (page 19) correct 4-bit interface initializing sample. (page 26) vdd conditions in electrical characteristics changed.(page 6~9) add more description for opt_ud option. (page 4) nov.2001 0.4 original feb.2001

▲Up To Search▲

Price & Availability of NT7605-BDW01

	To Download NT7605-BDW01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .